library ieee;
use ieee.std_logic_1164.all;
USE IEEE.std_logic_arith.ALL;

entity multiplier_tb is
	
end entity multiplier_tb;

architecture RTL of multiplier_tb is

    component multiplier is
    	port (
    		clk	: in bit;
        	dataIn : in bit_vector(31 downto 0);
        	loadM : in bit;
        	loadQ : in bit;
        	start : in bit;
        	reset : in bit;
        	dataOutHigh : out bit_vector(31 downto 0);
        	dataOutLow : out bit_vector(31 downto 0);
        	done : out bit
    	);
    end component;
	
	for all : multiplier use entity work.multiplier;
	
	signal clk : bit := '0';
	signal dataIn : bit_vector(31 downto 0) := "11111111111111111111111111111111";
	signal loadM, loadQ, start : bit := '0';
	signal reset : bit := '0';
	signal product_low, product_high : bit_vector(31 downto 0);
	signal done : bit;
	
	constant M1 : std_logic_vector(31 downto 0) :="11111111111111111111111111111011"; -- -5
	constant Q1 : std_logic_vector(31 downto 0) :="11111111111111111111111111111101"; -- -3

	--signal result1 : std_logic_vector(63 downto 0) := std_logic_vector(signed(M1)*signed(Q1));

	
begin

	clk <= not clk after 20 ns;
	
	UUT : multiplier port map (
		
		clk,
		dataIn,
		loadM,
		loadQ,
		start,
		reset,
		product_high,
		product_low,
		done
		
		);
	
	tb : PROCESS
		
	begin

		wait for 200 ns;
		
	--	dataIn <= "11111111111111111111111111111011";  ---    -5
	
		dataIn <= "00000000000000000000000000000000";
		

		loadM <= '1';
		wait for 100 ns;
		loadM <= '0';
		wait for 100 ns;
		dataIn <= "11111111111111111111111111111111";
		---dataIn <= "00000000000000000000000000001010";  -- 10
		wait for 100 ns;
		loadQ <= '1';
		wait for 100 ns;
		loadQ <= '0';
		wait for 100 ns;
		start <= '1';
			
		
		wait;
	    	
	end PROCESS;
	

end architecture RTL;
